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Spec #CR #Revision #Impacted VersionTarget ReleaseTitleWG TDoc #WG statusTSG TDoc #TSG statusNew Version
25.4330785-5.2.0Rel-5Correction for the DL DPDCH transmissionR3-022439agreedRP-020744approved5.3.0
25.4330782-5.2.0Rel-5Clarification for the inclusion of the DL Power Balancing Updated Indicator IER3-022429agreedRP-020766approved5.3.0
25.4330781-5.2.0Rel-5Correction for the definition of the MAC-hs Reordering Buffer Size IER3-022421agreedRP-020763approved5.3.0
25.4330780-5.2.0Rel-5Clarification to RACH for 1.28Mcps TDDR3-022412agreedRP-020754approved5.3.0
25.433077215.2.0Rel-5Clarification of the usage of HS-DSCH-RNTIR3-022567agreedRP-020765approved5.3.0
25.433077015.2.0Rel-5Addition of the second TDD Channelisation Code of HS-SCCH for the 1.28Mcps TDD option.R3-022561agreedRP-020767approved5.3.0
25.433076715.2.0Rel-5Clarification on the Minimum Spreading Factor for TDDR3-022554agreedRP-020754approved5.3.0
25.433076435.2.0Rel-5MAC-hs Window Size-agreedRP-020855approved5.3.0
25.4330757-5.2.0Rel-5Power Offset Values for HS-DPCCHR3-022319agreedRP-020768approved5.3.0
25.433075615.2.0Rel-5Measurement power offset signalling for HSDPAR3-022595 RP-020773approved5.3.0
25.4330755-5.2.0Rel-5SYNC_DL Code ID for 1.28Mcps TDDR3-022315agreedRP-020754approved5.3.0
25.433075325.2.0Rel-5Slot Format for 1.28Mcps TDDR3-022607agreedRP-020759approved5.3.0
25.4330751-5.2.0Rel-5Correction to RX Timing Deviation Lvalue rangeR3-022307agreedRP-020757approved5.3.0
25.4330749-5.2.0Rel-5Add UL SIR_target for Unsynchronized RL Reconfiguration in 1.28Mcps TDDR3-022303agreedRP-020758approved5.3.0
25.4330747-5.2.0Rel-5Alignment of Error Indication procedure text to the latest RNSAPR3-022297agreedRP-020754approved5.3.0