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Spec #CR #Revision #Impacted VersionTarget ReleaseTitleWG TDoc #WG statusTSG TDoc #TSG statusNew Version
25.4330822-4.7.0Rel-4Correction of PRACH Midamble for 1.28Mcps TDDR3-030172agreedRP-030059approved4.8.0
25.4330817-4.7.0Rel-4Corrections to DCH Combining in RL SETUP and RL ADDITIONR3-030151agreedRP-030066approved4.8.0
25.4330810-4.7.0Rel-4Midamble Configuration for Midamble Shift LCRR3-030120agreedRP-030071approved4.8.0
25.4330807-4.7.0Rel-4Correction for the Information Exchange Initiation procedureR3-030103agreedRP-030070approved4.8.0
25.433080514.7.0Rel-4Corrections to Channelisation Code TFCI Mapping for TDDR3-030262agreedRP-030082approved4.8.0
25.4330795-4.7.0Rel-4Clarification to 2nd Interleaving Mode for TDDR3-030062agreedRP-030069approved4.8.0
25.4330793-4.7.0Rel-4TPC Step Size for TDDR3-030058agreedRP-030072approved4.8.0
25.4330790-4.7.0Rel-4Clarification to DL Power definition for TDDR3-030052agreedRP-030068approved4.8.0