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Spec #CR #Revision #Impacted VersionTarget ReleaseTitleWG TDoc #WG statusTSG TDoc #TSG statusNew Version
25.433082725.3.0Rel-5Guaranteed Bit Rate for HSDPAR3-030320agreedRP-030076approved5.4.0
25.4330823-5.3.0Rel-5Correction of PRACH Midamble for 1.28Mcps TDDR3-030173agreedRP-030059approved5.4.0
25.4330818-5.3.0Rel-5Corrections to DCH Combining in RL SETUP and RL ADDITIONR3-030152agreedRP-030066approved5.4.0
25.4330811-5.3.0Rel-5Midamble Configuration for Midamble Shift LCRR3-030121agreedRP-030071approved5.4.0
25.433080915.3.0Rel-5T1 signalling for HSDPAR3-030303agreedRP-030074approved5.4.0
25.4330808-5.3.0Rel-5Correction for the Information Exchange Initiation procedureR3-030105agreedRP-030070approved5.4.0
25.433080615.3.0Rel-5Corrections to Channelisation Code TFCI Mapping for TDDR3-030263agreedRP-030082approved5.4.0
25.433080315.3.0Rel-5HS-SICH quality Reporting to support outer loop power controlR3-030311agreedRP-030080approved5.4.0
25.433080115.3.0Rel-5HS-DSCH: Addition of non HS-DSCH power measurement.R3-030283agreedRP-030081approved5.4.0
25.433080015.3.0Rel-5Clarification of HS-SCCH Power Offset usage in case of multiple HS-SCCHsR3-030300agreedRP-030073approved5.4.0
25.433079815.3.0Rel-5HS-PDSCH NBAP Corrections for TDDR3-030295agreedRP-030078approved5.4.0
25.433079725.3.0Rel-5HS-PDSCH Code and Timeslot Resource Assignment for TDDR3-030363agreedRP-030063approved5.4.0
25.4330796-5.3.0Rel-5Clarification to 2nd Interleaving Mode for TDDR3-030063agreedRP-030069approved5.4.0
25.4330794-5.3.0Rel-5TPC Step Size for TDDR3-030059agreedRP-030072approved5.4.0
25.433079235.3.0Rel-5Correction to DL Tx Power for TDDR3-030360agreedRP-030077approved5.4.0
25.4330791-5.3.0Rel-5Clarification to DL Power definition for TDDR3-030053agreedRP-030068approved5.4.0