WI # 21005 - RInImp-FSVHCRTDD

Name:

FS on Analysis on Higher Chip Rates for UTRA TDD evolutions

Acronym:

RInImp-FSVHCRTDD

Effective Acronym:

RInImp-FSVHCRTDD

WI Level:

Building Block (2nd level)

Type:

Work Item

Status:

Awaiting approval

Release:

Rel-6

Start date:

2002-09-06

End date:

2004-09-14

Remarks (1)

Creation date	Author	Remark


2015-01-22 12:41 UTC		Study finished at RP#25

Parent Work Item:

3 - Rel-6 RAN Feasibility Studies

Child Work Items:

WI UID	WI name


No records to display.

Responsible group(s):

Rapporteur(s):

mbeale@ipwireless.com (IPWireless)

Latest WID version:

TSG Approval meeting:

PCG Approval meeting:

TSG Stopped meeting:

PCG Stopped meeting:

See Specifications specifically resulting from this Work Item

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